1. Field of the Invention
Embodiments of the present invention relate to the field of testing electrical connections and traces of an electronic device and a printed circuit board. More particularly, embodiments of the present invention relate to the use and integration of parallel capacitors with external or embedded capacitors in a test module to test the connections between a printed circuit board, or a motherboard, and a device socket.
2. Discussion of Related Art
It is valuable to be able to test the electrical connections between the sockets of electronic devices and a printed circuit board (PCB) or motherboard, as well as the integrity of the traces within the testing equipment, socket, and PCB. The inspection of the socket connections to a PCB is valuable because open solder joints, broken pins, springs, or other poor connections on any of the signal connections may result in the processor malfunctioning, or failing to boot altogether. Openings on the power and ground connections may cause the processor to malfunction under a heavy load, cause hot spots due to excessive current in the connected power and ground pins, or cause reliability issues over time at the customer end.
The type of socket used varies based on how a device is designed to connect to a socket and a PCB. In the past, devices were typically connected to a socket and a PCB by through pins. Therefore, pinned grid array sockets having pins were used. Devices have evolved from through board pins to the surface mounting of a device to a socket and PCB. A device that is designed to be surface mounted has pads, or flat conductive discs, on its packaging. For a ball grid array (BGA) device there will be solder bumps on the pads for connection with a BGA socket. The solder bumps typically fit into grips on a BGA socket for connection to a PCB. A land grid array (LGA) device only has pads. The pads of an LGA require a socket containing springs or some other type of conductive trace to connect the device to the PCB. Human visual inspection of the solder joints within a BGA socket or the conductive traces within a LGA socket is not possible. Therefore, test modules that connect to the socket to test its connection to a PCB have been developed.
Testing the connections between a socket and a PCB can be performed in a number of ways. The testing methods can be divided into two groups. One group is the “power-up” tests that require powering up the board and device. The other group is the “no-power” tests that do not require powering up the board and devices. In a “no-power” test only the equipment that is used for transmitting or receiving an electrical signal has power. The “no-power” tests are preferred because they do not require turning on the individual devices on a PCB or extensive knowledge about the devices in order to determine that the correct device has been properly connected, oriented, and soldered. “No-power” tests also offer the advantages of testing connections during assembly and of compatibility with both in-circuit testers (ICT) and Manufacturing Defect Analyzer (MDA) testers. Compatibility with MDA testers is valuable because they are widely used by Far East board manufacturing.
One prevalent “no-power” test is the Agilent™TestJet™ technique. This technique takes advantage of the lead frame present in most socket connectors. The lead frame is a metal framework that includes the devices input, output, and power traces and their extensions up to the point where an IC or a socket connector is attached. As used in this description, the term trace refers to the conductive element (like a wire or pin) within a component such as a PCB or a socket. The size and shape of the lead frame is fairly consistent between devices and vendors. The TestJet™ technique for testing socket connections uses a test module adapted to the particular type of socket to be tested (for example, if a pin grid array socket is being tested the test module will have pins) and an external sensing plate that is suspended above the socket, and separated from the lead frame. The lead frame and the external plate form a small capacitance that can be measured by the ICT or MDA testers via the application of an AC source. Because each socket connection between a socket and a PCB consists of a part of the lead frame, each connection can be detected as a separate capacitance value for testing purposes.
When a socket connection is not properly connected to the PCB there will be an additional capacitor in series with the TestJet™ capacitor. This additional capacitance exists because there is a tiny air gap within the socket connection trace. The series combination of the TestJet™ capacitor and this additional pin capacitor is smaller than either capacitor. Therefore, the TestJet™ technique measures the capacitance at each socket connection, and identifies each socket connection that has a capacitance smaller than the expected capacitance for that socket connection. By this technique, poor connections and traces within the PCB and socket can be detected. But, the TestJet™ technique has limitations in its ability to detect traces (or pins) within the PCB that are tied, such as the commonly tied power or ground traces. This is because the TestJet™ tests in serial mode, testing one trace at one socket connection at a time. If the trace being tested is a tied trace that is broken or has an open solder joint, the test signal will still go through, and the expected capacitance will be read for the tied trace being tested, even if only one of the tied traces is intact and has a good solder joint. The TestJet™ can thus fail to detect broken traces or open solder joints on tied traces. The TestJet™ also has difficultly detecting weak signals due to shorter signal propagation paths in current generations of sockets.
Another testing device that could be used to detect the integrity of electrical connections and traces is the FET TCT (Field Effect Transistor Through Connector Testing) (Published patent application U.S. 2003/0057981 A1, Assigned to Intel Corporation). The FET TCT is a “power-up” test because it requires the board under test (BUT) to be properly powered-up prior to testing. The FET TCT consists of an array of FET pairs on a test module. One FET in such a pair connects a single signal trace to a single power trace and the other FET connects the signal trace to a single ground trace. Multiple FET pairs are used to connect all signal traces to independent power and ground traces. The gates of the high side FETS are connected to a common control trace within the test module and the gates of the low side FETS are connected to a second control trace within the test module. When the control signal for the high side FET is driven high by the tester, a continuity path should exist through the power trace, the high side FET, and back through the signal trace. If all traces were soldered properly, a digital high state should be measured on the signal traces when the high side FET's are active. When the control signal for the low side FET is driven high by the tester, a continuity path should exist through the signal trace, the low side FET, and back through the ground trace. If all traces were soldered properly, a digital low state would be measured on the signal trace, or the power/ground trace used by that FET pair.
Although the FET TCT can detect the solder connections and traces of tied signal and ground traces, it requires an attachment to every signal, ground, and power trace. Because of this requirement, the FET TCT must have a large footprint that can cause fixture design issues and difficulty of use. As the number of traces increases and devices are further scaled down, the FET TCT will become even larger and more difficult to use. Additionally, the FET TCT is a power-up test that is only compatible with an in-circuit tester and not an MDA tester type that is widely used by Far East board manufacturing. The FET TCT is also not easily compatible with a land grid array (LGA) CPU because an LGA is typically quite fragile and a bulky FET TCT test module could cause significant harm.